Filter and downsample input signals (HDL Coder)
The FIR Decimation block is available with DSP System Toolbox™.
For information about the simulation behavior and block parameters, see FIR Decimation.
HDL Coder™ supports Coefficient source options Dialog parameters, Filter object, or Auto.
Observe the following limitations for FIR Decimation filters:
HDL Coder supports SerialPartition only
for the FIR Direct Form structure.
Accumulator reuse is not supported.
Distributed Arithmetic properties DALUTPartition and DARadix are supported for the following filter structures.
| Architecture | Supported FIR Structures |
|---|---|
| default, Distributed Arithmetic (DA) | Direct form |
When you use AddPipelineRegisters, registers are placed based on the filter structure. The pipeline register placement determines the latency.
| Filter Structure | Pipeline Register Placement | Latency (clock cycles) |
|---|---|---|
| Direct form | One pipeline register is added between levels of a tree-based adder, and one is added after the products. | ceil(log2(NZ)). NZ is
the number of non-zero coefficients. |
| Direct form transposed | No pipelining is added. | 0 |
Insert a pipeline register between stages of computation in a filter. See also AddPipelineRegisters.
Specify the use of canonical signed digit (CSD) optimization
to decrease filter area by replacing coefficient multipliers with
shift-and-add logic. When you choose a fully parallel filter implementation,
you can set CoeffMultipliers to csd or factored-csd.
The default is multipliers, which retains multipliers
in the HDL. See alsoCoeffMultipliers.
Specify distributed arithmetic partial-product LUT partitions as a vector of the sizes of each partition. The sum of all vector elements must be equal to the filter length. The maximum size for a partition is 12 taps. Set DALUTPartition to a scalar value equal to the filter length to generate DA code without LUT partitions. See also DALUTPartition.
Specify how many distributed arithmetic bit sums are computed
in parallel. A DA radix of 8 (2^3) generates a
DA implementation that computes three sums at a time. The default
value is 2^1, which generates a fully serial DA
implementation. See also DARadix.
Specify the number of pipeline stages to add at filter multiplier inputs. See also MultiplierInputPipeline.
Specify the number of pipeline stages to add at filter multiplier outputs. See also MultiplierOutputPipeline.
Specify partitions for partly serial or cascade-serial filter implementations as a vector of the lengths of each partition. For a fully serial implementation, set this parameter to the length of the filter. See also SerialPartition.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
You must set Initial conditions to zero. HDL code generation is not supported for nonzero initial states.
Vector and frame inputs are not supported for HDL code generation.
When you select Dialog parameters, the following fixed-point options are not supported for HDL code generation:
Slope and Bias scaling
CoeffMultipliers options are supported only when using a fully parallel architecture. When you select a serial architecture, CoeffMultipliersis hidden from the HDL Block Properties dialog box.