Downsample

Resample input at lower rate by deleting samples (HDL Coder)

Description

The Downsample block is available with DSP System Toolbox™.

For information about the simulation behavior and block parameters, see Downsample.

Best Practices

It is good practice to follow the Downsample block with a unit delay. Doing so prevents the code generator from inserting an extra bypass register in the HDL code.

See also Multirate Model Requirements for HDL Code Generation.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline

Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.

InputPipeline

Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.

OutputPipeline

Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.

Complex Data Support

This block supports code generation for complex signals.

Restrictions

  • For Frame based mode, select Maintain input frame size.

  • For Sample based mode, select Allow multirate.

With these block settings, if Sample offset is set to 0, Initial conditions has no effect on generated code.

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