Restore ordering of symbols that were permuted using shift registers (HDL Coder)
The Convolutional Deinterleaver block is available with Communications System Toolbox™.
For information about the simulation behavior and block parameters, see Convolutional Deinterleaver.
The default implementation for the Convolutional Deinterleaver
block is shift register-based. If you want to suppress generation
of reset logic, set the implementation parameter ResetType to'none'.
When you set ResetType to'none',
reset is not applied to the shift registers. When registers are not
fully loaded, mismatches between Simulink® and the generated code
occur for some number of samples during the initial phase. To avoid
spurious test bench errors, determine the number of samples required
to fill the shift registers. Set the Ignore output data
checking (number of samples) option accordingly. (If you
are using the command-line interface, you can use the IgnoreDataChecking property
for this purpose.)
When you select the RAM implementation
for a Convolutional Deinterleaver block, HDL Coder™ uses RAM resources
instead of shift registers.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
Suppress reset logic generation. The default is default,
which generates reset logic. See also ResetType.
When you select the RAM implementation:
Double or single data types are not supported for either input or output signals.
You must set Initial conditions for the block to zero.
At least two rows of interleaving are required.