Decimate signal using Cascaded Integrator-Comb filter (HDL Coder)
The CIC Decimation block is available with DSP System Toolbox™.
For information about the simulation behavior and block parameters, see CIC Decimation.
HDL Coder™ supports Coefficient source options Dialog parameters and Filter object.
When you use AddPipelineRegisters, registers are placed based on the filter structure. The pipeline register placement determines the latency.
| Pipeline Register Placement | Latency (clock cycles) |
|---|---|
| A pipeline register is added between the comb stages of the differentiators. | NS-1, where NS is number
of sections (at the output side). |
Insert a pipeline register between stages of computation in a filter. See also AddPipelineRegisters.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
Vector and frame inputs are not supported for HDL code generation.
When you select Dialog parameters,
the Filter Structure option Zero-latency
decimator is not supported for HDL code generation.
From the Filter Structure drop-down list, select Decimator.