Documentation

FPGA Synthesis and Analysis Tasks Overview

The tasks in the FPGA Synthesis and Analysis folder let you run third-party FPGA synthesis and analysis tools without leaving the HDL Workflow Advisor environment. Tasks in this category include:

• Creation of FPGA synthesis projects for supported FPGA synthesis tools

• Launching supported FPGA synthesis tools to perform synthesis, mapping, and place/route tasks

• Annotation of your original model with critical path information obtained from the synthesis tools

Note:   A supported synthesis tool must be installed, and the synthesis tool executable must be on the system path to perform the tasks in the FPGA Synthesis and Analysis folder. See Third-Party Synthesis Tools and Version Support for more information.

Creating a Synthesis Project

The Create Project task does the following:

• Realizes a synthesis project for the tool from the previously generated HDL code

• Creates a link to the project files in the Result subpane

• (Optional) Launches the synthesis tool and opens the synthesis project

The following figure shows the Create Project task in an enabled state, after HDL code generation.

The Create Project task parameters are:

• Project directory: The HDL Workflow Advisor writes the project files to a subfolder of the hdlsrc folder. You can enter the path to an alternative folder, or click the Browse button to navigate to the desired folder.

• Additional source files: To include HDL files (or other synthesis files, such as UCF or SDC files) that the code does not generate in your synthesis project, enter the full path to the desired files. Click the Add button to locate each file.

The following figure shows the HDL Workflow Advisor after passing the Create Project task. If you want to view the synthesis project, click the hyperlink in the Result subpane. This link launches the synthesis tool and opens the synthesis project.

Performing Synthesis, Mapping, and Place and Route

Performing Logic Synthesis

The Perform Logic Synthesis task does the following:

• Launches the synthesis tool in the background.

• Opens the previously generated synthesis project, compiles HDL code, synthesizes the design and emits netlists and related files.

• Displays a synthesis log in the Result subpane.

The Perform Logic Synthesis task does not have input parameters. The following figure shows the HDL Workflow Advisor after passing the Perform Logic Synthesis task.

Performing Mapping

The Perform Mapping task does the following:

• Launches the synthesis tool in the background.

• Runs a mapping process that maps the synthesized logic design to the target FPGA.

• Emits a circuit description file for use in the place and route phase.

• Displays a log in the Result subpane.

If your tool does not support early timing estimation, you can enable Skip pre-route timing analysis. When this option is enabled, the Annotate Model with Synthesis Result task sets Critical path source to post-route.

The following figure shows the HDL Workflow Advisor after passing the Perform Mapping task.

Performing Place and Route

The Perform Place and Route task does the following:

• Launches the synthesis tool in the background.

• Runs a place and route process using the circuit description produced by the mapping process, and emits a circuit description suitable for programming an FPGA.

• Emits pre- and post-routing timing information for use in critical path analysis and back annotation of your source model.

• Displays a log in the Result subpane.

Unlike other tasks in the HDL Workflow Advisor hierarchy, Perform Place and Route is optional. If you select Skip this task in the right-hand pane, the HDL Workflow Advisor executes the workflow, but omits the Perform Place and Route task, marking it Passed. Select Skip this task if you prefer to do place and route work manually.

If the Perform Place and Route task fails, you can select Ignore place and route errors to continue to the Annotate Model with Synthesis Result task. This allows you to use post-mapping timing results to find critical paths in your model even if place and route fails.

The following figure shows the HDL Workflow Advisor after passing the Perform Place and Route task.

Annotating Your Model with Critical Path Information

The Annotate Model with Synthesis Result task helps you identify critical paths in your model. In this task, you can analyze pre- or post-routing timing information from the Perform Place and Route task and visually highlight one or more critical paths in your model.

The following figure shows the Annotate Model with Synthesis Result task in an enabled state.

The task parameters are:

• Critical path source: Select pre-route or post-route. The default is pre-route.

  Note that the pre-route option is unavailable when Skip pre-route timing analysis is enabled in the Perform Mapping task.

• Critical path number: You can annotate up to 3 critical paths. Select the number of paths you want to annotate. The default is 1.

• Show all paths: Show critical paths, including duplicate paths. The default is off.

• Show unique paths: Show only the first instance of a path that is duplicated. The default is off.

• Show delay data: Annotate the cumulative timing delay on each path. The default is on.

• Show ends only: Show the endpoints of each path, but omit the connecting signal lines. The default is off.

When the Annotate Model with Synthesis Result task runs to completion, HDL Coder™ displays the DUT with critical path information highlighted. The following figure shows a subsystem after critical path annotation. Using default options, the annotation includes the endpoints, signal lines, and delay data.

After the Annotate Model with Synthesis Result task runs to completion, the HDL Workflow Advisor enables the Reset Highlighting button in the Action subpane. When you click this button, the HDL Workflow Advisor:

• Clears critical path annotations from the model.

• Resets the Annotate Model with Synthesis Result task.