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This example shows how to generate HDL code from a Simulink^® model using the HDL Workflow Advisor.

Create Working Folder and Copy Model

Prepare the model you use in this example, sfir_fixed, for code generation.

This example uses the Xilinx^® ISE synthesis tool, and assumes that your synthesis tool path is set up. You can also follow this example using Altera^® Quartus II.

1. Start MATLAB^®.

2. Create a folder named sl_hdlcoder_work. For example:

   mkdir C:\work\sl_hdlcoder_work
   

   You use sl_hdlcoder_work to store a local copy of the example model and to store folders and code generated by HDL Coder™. The location of the folder does not matter, except that it should not be within the MATLAB folder tree.

3. Make the sl_hdlcoder_work folder your working folder. For example:

   cd C:\work\sl_hdlcoder_work
   

4. Open the sfir_fixed model.

   sfir_fixed

5. Save a copy of sfir_fixed in your sl_hdlcoder_work folder.

Generate Code Using the HDL Workflow Advisor

• Right-click the symmetric_fir subsystem and select HDL Code > HDL Workflow Advisor.

• In the Set Target > Set Target Device and Synthesis Tool step, for Synthesis tool, select Xilinx ISE and click Run This Task.

  

• Right-click Prepare Model For HDL Code Generation and select Run All. The HDL Workflow Advisor checks the model for code generation compatibility.

• In the HDL Code Generation > Set Code Generation Options > Set Basic Options step, select the following options, then click Apply:

  • For Language, select Verilog.

  • Enable Generate traceability report.

  • Enable Generate resource utilization report.

• View the options available in the Optimization and Coding style tabs. You can use these options to modify the implementation and format of the generated code.

• Right-click the HDL Code Generation > Generate RTL Code and Testbench step, and select Run to Selected Task.

  The code generation report, which includes the resource utilization and traceability reports, opens automatically. The resource utilization report shows the hardware resources your design implementation is using. The traceability report enables you to navigate between your model and the generated code.

  

Perform FPGA Synthesis and Analysis

1. In the FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and Route task, unselect Skip this task and click Apply.

2. Right-click Annotate Model with Synthesis Result and select Run to Selected Task.

3. View the annotated critical path in the model.

   The critical path is colored cyan.