The HDL Workflow Advisor is a tool that supports and integrates the stages of the FPGA design process, such as:
Checking the Simulink® model for HDL code generation compatibility
Automatically fixing model settings that are incompatible with HDL code generation
Generation of RTL code, RTL test bench, a cosimulation model, or a combination of these
Synthesis and timing analysis through integration with third-party synthesis tools
Back annotation of the Simulink model with critical path and other information obtained during synthesis
Complete automated workflows for selected FPGA development target devices and Simulink Real-Time™, including FPGA-in-the-Loop simulation