Using IP Core Generation Workflow with Altera FPGA Boards: Arrow DECA MAX 10 FPGA evaluation kit
This example shows how to use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Altera® parts without an embedded ARM® processor present, but which still utilize the HDL Coder™ generated AXI interface to control the DUT. This example will use the Arrow DECA MAX 10 FPGA evaluation kit and a Altera Qsys™ JTAG to Avalon Master Bridge IP in the reference design to access the HDL Coder™ generated DUT registers.
Requirements
Altera Quartus™ II 15.1
Arrow DECA MAX 10 FPGA evaluation kit
HDL Coder™ support package for Altera FPGA Boards
Arrow DECA MAX 10 FPGA evaluation kit
Example Reference Designs
There are many designs which will benifit from using the HDL Coder™ IP Core Generation Workflow without using either an embedded ARM® processor or an Embedded Coder™ Support Package, but which still leaverages the HDL Coder™ generated AXI4 registers. These designs include:
Nios® II + HDL Coder™ IP Core
PCIe® Endpoint + HDL Coder™ IP Core
JTAG Master + HDL Coder™ IP Core
For this example, you will use a JTAG Master to access the HDL Coder™ generated registers. The JTAG Master design can be used on its own to tune values on a system, or it can be used as a starting point for other designs which treat the HDL Coder™ IP Core as a memory mapped peripheral.
The following is a system level diagram for this JTAG Master system:
The reference design, "Altera JTAG to AXI Master", uses Qsys™ IP for the JTAG to AXI Master and therefore requires using the Altera® System Console to issue reads and writes:
Example Reference Design plugin_rd.m
The plugin_rd.m for this reference design is shown below:
function hRD = plugin_rd() % Reference design definition
% Copyright 2016 The MathWorks, Inc.
% Construct reference design object hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Altera QUARTUS II');
hRD.ReferenceDesignName = 'Altera JTAG to AXI Master'; hRD.BoardName = 'Arrow DECA MAX 10 FPGA evaluation kit';
% Tool information hRD.SupportedToolVersion = {'15.1'};
%% Add custom design files % add custom Qsys design hRD.addCustomQsysDesign('CustomQsysPrjFile', 'system_soc.qsys'); hRD.CustomConstraints = {'system_soc.sdc','system_setup.tcl'};
%% Add interfaces % add clock interface hRD.addClockInterface( ... 'ClockConnection', 'altpll_0.c0', ... 'ResetConnection', 'clk_0.clk_reset',... 'DefaultFrequencyMHz', 100);
% add AXI4 slave interfaces hRD.addAXI4SlaveInterface( ... 'InterfaceConnection', 'master_0.master', ... 'BaseAddress', '0x0000_0000',... 'InterfaceType', 'AXI4',... % [ 'AXI4-Lite'| 'AXI4' ] 'InterfaceID', 'JTAG AXI4 Interface'); % string name in interface table
% Specify Embedded Coder Support Pacakge to use for Software Interface hRD.EmbeddedCoderSupportPackage = hdlcoder.EmbeddedCoderSupportPackage.None; % [ None | Zynq | AlteraSoC ]
Execute the IP Core Workflow
Using the above reference design you will generate an HDL IP Core that blinks LEDs on the DECA board. You will then use the Altera® System Console Tcl interfaces to read and write the DUT registers. The files used in the following demonstration are located at:
matlab/toolbox/hdlcoder/hdlcoderdemos/customboards/DECA
1. Add the JTAG to AXI Master reference design files to the MATLAB path using the command:
>> addpath(fullfile(matlabroot,'toolbox','hdlcoder','hdlcoderdemos','customboards','DECA'));
2. Set up the Altera Quaruts™ II tool path by using the following command:
>> hdlsetuptoolpath('ToolName', 'Altera QUARTUS II', 'ToolPath', 'C:\altera\15.1\quartus\bin64\quartus.exe');
Use your own Altera Quartus™ II installation path when executing the command.
3. Open the Simulink model that implements LED blinking using the command:
open_system('hdlcoder_led_blinking')
4. Launch HDL Workflow Advisor from the hdlcoder_led_blinking/led_counter subsystem by right-clicking the led_counter subsystem, and selecting HDL Code > HDL Workflow Advisor.
5. Select reference design from the drop down in step 1.2
6. Assign register ports to the "JTAG AXI4 Interface". These will then be accessible at the hex offset shown in the table.
7. Run the remaining steps in the workflow to generate a bitstream and program the target device.
Notice that unlike the AlteraSoC-based reference design, there is no 'Generate Software Inteface Model' task. In the reference design "plugin_rd.m", you can disable this task using the following command:
% Disable 'Generate Software Inteface Model' task hRD.EmbeddedCoderSupportPackage = hdlcoder.EmbeddedCoderSupportPackage.None; %None
Determining Adresses from the IP Core Report
The Base Address for an HDL Coder™ IP Core is defined in the reference design plugin_rd.m with the following command:
% add AXI4 slave interfaces hRD.addAXI4SlaveInterface( ... 'InterfaceConnection', 'master_0.master', ... 'BaseAddress', '0x0000_0000',... 'InterfaceType', 'AXI4',... 'InterfaceID', 'JTAG AXI4 Interface');
For this design, the base address is 0x0000_0000. The offsets can be found in the IP Core Report Register Address Mapping table:
Qsys System Console Tcl Commands for AXI Read and Write
Before we open a System Console, lets look at the basic commands to issue reads and writes. There are a number of flavors of Qsys read and write methods, but we will use the following since all HDL Coder™ generated IP Core registers are currently 32-bits:
% master_write_32 <service-path> <start-address> <list-of-32-bit-values> % master_read_32 <service-path> <start-address> <size-in-multiples-of-32-bits>
For example, assume we would like to write the 32 bit hex value '0x12345678' to the IP Core register defined by offset '0x100' using a previously defined service path stored in the variable $jtag, we would use the following command
% master_write_32 $jtag 0x100 0x12345678
For more information on these commands you can view help at any time via the following Tcl commands:
% help master_write_32 % help master_read_32
or see the Altera documentation ug_system_console.pdf for more details.
Qsys System Console
Before you can generate reads and writes, you must first launch a System Console and open a connection to the JTAG Master that will issue the register reads and writes. Refer again to the system diagram below:
To open a connection to JTAG Master, you will first need to set a variable that stores the serivce path (in this case, there is only one master):
% set jtag [lindex [get_servce_paths master] 0]
Then use the viable to open the JTAG Master in master mode
% open_service master $jtag
Now launch the Altera® System Console directly, entering the above commands to open the jtag master:
>> system('C:\altera\15.1\quartus\bin64\sopc_builder\bin\system-console&')
When you are done using the JTAG Master, make sure to close the connection using the following Tcl command:
close_service master $jtag
Summary
Using a JTAG to AXI Master is a simple way to interface with HDL Coder™ IP core registers in systems which do not have an embedded ARM® processor, such as the MAX 10. This can be used as first step to debug stand alone HDL Coder™ IP cores, used prior to hand coding software for soft processors, such as Nios® II, or as an easy way to tune parameters on a running system.