Single Precision Floating Point Example: Field-Oriented Control Algorithm

This example also uses:

Simscape Power Systems

In this example you will review a Field-Oriented Control (FOC) algorithm for a Permanent Magnet Synchronous Machine (PMSM) implemented using single-precision floating-point representation.

Introduction

You have seen fixed-point version of this design in FOC Model (Fixed-Point) that takes a deep dive into how to implement current control algorithm using fixed-point types. The model was converted to fixed-point before generating HDL. Fixed-Point conversion was a necessary step before HDL code generation.

However starting in R2016b release HDLCoder supports floating-point single precision types and this demo shows design considerations when generating code from the floating-point single precision models.

Both the demos use same testbench model 'hdlcoderFocCurrentTestBench' with reference block pointing to DUT implemented in fixed-point or floating-point.

Verify Behavior through Simulation

hasSimPowerSystems = license ('test', 'Power_System_Blocks');
if hasSimPowerSystems
   open_system('hdlcoderFocCurrentTestBench')

   % set single-precision floating-point model in the testbench
   set_param('hdlcoderFocCurrentTestBench/Controller', 'ModelName', 'hdlcoderFocCurrentFloatHdl');

   set_param('hdlcoderFocCurrentTestBench','IgnoredZcDiagnostic','none');
   sim('hdlcoderFocCurrentTestBench')
   set_param('hdlcoderFocCurrentTestBench','IgnoredZcDiagnostic','warn');
end

Sometimes you may want to start and stay in floating-point to target HDL for the following reasons

Your algorithms have large or unknown dynamic ranges (for example integrators in feedback loops)
Your algorithm uses operations that are difficult to design in fixed-point (ex: atan2)

In the fixed-point version of the example hdlcoderFocCurrentFloatHDL.slx you will notice that several fixed-point rounding and saturation decisions are made to preserve numerical behavior of the algorithm. For example the block 'hdlcoderFocCurrentFixptHdl/FOC_Current_Control/DQ_Current_Control/D_Current_Control/Saturate' which is a saturation block has been placed in the integrator loop so that results do not overflow due to accumulation in the loop.

Sometimes the task of fixed-point conversion could take several weeks to months with multiple levels of algorithm re-validation. It may also lead to undesirable loss of precision which may not be acceptable for some mission critical applications requiring very high accuracy. In these situations you can choose to using native floating point synthesis features available in HDLCoder.

For example, the algorithm setup in single-precision version of the algorithm does not require additional rounding and saturation blocks and settings as can be seen in the floating-point version of the model. 'hdlcoderFocCurrentFloatHdl/FOC_Current_Control/DQ_Current_Control/D_Current_Control'

Salient features of Native Floating Point support.

Here are the key features of the single-precision support available in HDL Coder

Vendor independent and target agnostic RTL for FPGA and/or ASIC design
Full range of IEEE-754 features including optional support for denormals and support for inf and nan data types and rounding modes.
Extensive math block (add,mul,div,recip,log,exp,sqrt, rsqrt) and trigonometric block (sin, cos, sincos, atan, atan2) support

load_system('hdlcoderFocCurrentFloatHdl');
open_system('hdlcoderFocCurrentFloatHdl/FOC_Current_Control')

Generate HDL Code for Control Algorithm

% You can generate and review the HDL code for the controller.
%
hdlset_param('hdlcoderFocCurrentFloatHdl', 'FloatingPointTargetConfiguration', hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT'));
makehdl('hdlcoderFocCurrentFloatHdl/FOC_Current_Control');

### Generating HDL for 'hdlcoderFocCurrentFloatHdl/FOC_Current_Control'.
### Starting HDL check.
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 0: 5 cycles.
### Clock-rate pipelining results can be diagnosed by running this script: <a href="matlab:run('hdlsrc/hdlcoderFocCurrentFloatHdl/highlightClockRatePipelining')">hdlsrc/hdlcoderFocCurrentFloatHdl/highlightClockRatePipelining.m</a>
### To clear highlighting, click the following MATLAB script: <a href="matlab:run('hdlsrc/hdlcoderFocCurrentFloatHdl/clearhighlighting.m')">hdlsrc/hdlcoderFocCurrentFloatHdl/clearhighlighting.m</a>
### Generating new validation model: <a href="matlab:open_system('gm_hdlcoderFocCurrentFloatHdl_vnl')">gm_hdlcoderFocCurrentFloatHdl_vnl</a>.
### Validation model generation complete.
### Begin VHDL Code Generation for 'hdlcoderFocCurrentFloatHdl'.
### MESSAGE: The design requires 800 times faster clock with respect to the base rate = 2e-05.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/DQ_Current_Control/D_Current_Control/Saturate_Output/nfp_uminus_comp as hdlsrc/hdlcoderFocCurrentFloatHdl/nfp_uminus_comp.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/DQ_Current_Control/D_Current_Control/nfp_relop_comp as hdlsrc/hdlcoderFocCurrentFloatHdl/nfp_relop_comp.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/DQ_Current_Control/D_Current_Control/nfp_relop_comp as hdlsrc/hdlcoderFocCurrentFloatHdl/nfp_relop_comp_block.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/DQ_Current_Control/D_Current_Control/Saturate_Output as hdlsrc/hdlcoderFocCurrentFloatHdl/Saturate_Output.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/Clarke_Transform/nfp_mul_comp as hdlsrc/hdlcoderFocCurrentFloatHdl/nfp_mul_comp.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/DQ_Current_Control/D_Current_Control/nfp_sub_comp as hdlsrc/hdlcoderFocCurrentFloatHdl/nfp_sub_comp.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/Clarke_Transform/nfp_add_comp as hdlsrc/hdlcoderFocCurrentFloatHdl/nfp_add_comp.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/DQ_Current_Control/D_Current_Control/nfp_relop_comp as hdlsrc/hdlcoderFocCurrentFloatHdl/nfp_relop_comp_block1.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/DQ_Current_Control/D_Current_Control as hdlsrc/hdlcoderFocCurrentFloatHdl/D_Current_Control.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/DQ_Current_Control as hdlsrc/hdlcoderFocCurrentFloatHdl/DQ_Current_Control.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/Inverse_Clarke_Transform/nfp_pow2_comp as hdlsrc/hdlcoderFocCurrentFloatHdl/nfp_pow2_comp.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/Space_Vector_Modulation/nfp_relop_comp as hdlsrc/hdlcoderFocCurrentFloatHdl/nfp_relop_comp_block2.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/Space_Vector_Modulation/nfp_relop_comp as hdlsrc/hdlcoderFocCurrentFloatHdl/nfp_relop_comp_block3.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/Space_Vector_Modulation as hdlsrc/hdlcoderFocCurrentFloatHdl/Space_Vector_Modulation.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/Inverse_Clarke_Transform/nfp_add2_comp as hdlsrc/hdlcoderFocCurrentFloatHdl/nfp_add2_comp.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/Inverse_Clarke_Transform as hdlsrc/hdlcoderFocCurrentFloatHdl/Inverse_Clarke_Transform.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/Inverse_Park_Transform as hdlsrc/hdlcoderFocCurrentFloatHdl/Inverse_Park_Transform.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/Subsystem/SinCosTrig/nfp_sincos_comp as hdlsrc/hdlcoderFocCurrentFloatHdl/nfp_sincos_comp.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/Subsystem/SinCosTrig as hdlsrc/hdlcoderFocCurrentFloatHdl/SinCosTrig.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/Subsystem as hdlsrc/hdlcoderFocCurrentFloatHdl/Subsystem.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/Park_Transform as hdlsrc/hdlcoderFocCurrentFloatHdl/Park_Transform.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control/Clarke_Transform as hdlsrc/hdlcoderFocCurrentFloatHdl/Clarke_Transform.vhd.
### Working on FOC_Current_Control_tc as hdlsrc/hdlcoderFocCurrentFloatHdl/FOC_Current_Control_tc.vhd.
### Working on hdlcoderFocCurrentFloatHdl/FOC_Current_Control as hdlsrc/hdlcoderFocCurrentFloatHdl/FOC_Current_Control.vhd.
### Generating package file hdlsrc/hdlcoderFocCurrentFloatHdl/FOC_Current_Control_pkg.vhd.
### Generating HTML files for code generation report at <a href="matlab:web('/tmp/BR2016bd_418663_21018/publish_examples1/tp7003a755_8bc8_4b82_9fd0_5d681546ac7e/hdlsrc/hdlcoderFocCurrentFloatHdl/html/hdlcoderFocCurrentFloatHdl/hdlcoderFocCurrentFloatHdl_codegen_rpt.html');">hdlcoderFocCurrentFloatHdl_codegen_rpt.html</a>
### Creating HDL Code Generation Check Report file:///tmp/BR2016bd_418663_21018/publish_examples1/tp7003a755_8bc8_4b82_9fd0_5d681546ac7e/hdlsrc/hdlcoderFocCurrentFloatHdl/FOC_Current_Control_report.html
### HDL check for 'hdlcoderFocCurrentFloatHdl' complete with 0 errors, 0 warnings, and 2 messages.
### HDL code generation complete.

The generated code fully implements IEEE single precision operators for various floating-point operators (add, sub, mul, uminus, pow2 and relop comps) used in the model.

Please refer to documentation for full native floating-point capabilities available in HDLCoder. See link here <matlab:helpview(fullfile(docroot,'hdlcoder/ug/native-floating-point-support.html')).

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